In communications systems, data is often communicated between devices over a channel. The channel may be a wired connection such as a PCI Express, or other cable, or a wireless connection. A transmitter sending data is located physically apart from the receiving device. The transmitter and receiver may have a local clock or timing generator such as a phase locked loop (PLL). In many systems the PLL generates a local version of a clock that may correspond to a system or bus clock. The PCI Express standard, as one non-limiting example, uses serial data with an embedded clock signal in the data stream. This approach has advantages in limiting the number of signal wires required, and the transmitter timing may be recovered at the receiver by use of any one of several known clock and data recovery (CDR) approaches which can extract the clock using edge detection and typically, a phase locked loop (PLL) circuit that is synchronized to the detected edges. However, due to the variance in integrated circuit parameters and processes, the local clock may have a frequency that varies from the clock formed in other devices. This results in a frequency difference between the transmitter and the receiver device that cannot be easily eliminated, due to the practical limitations on the circuits.
One approach to receiving data from a remote transmitter over a channel where the transmitter and receiver are clocked on potentially differing local clocks is to use an “elastic” buffer. Often an elastic buffer is used to buffer the data stream from the data bus into the receiver. The available depth of the elastic buffer must be large enough to attempt to prevent two erroneous conditions: overflow (when too many data words are received from the transmitter before the receiver can empty the buffer, thus the buffer overflows) and underflow (too few data words are received from the transmitter, and thus the receiver has emptied the buffer before more data words are received.) In most expected conditions, there should be room for the transmitter to write new data words into the buffer, likewise the receiver should normally have data available to it in the buffer for reading out, so that both the transmitter and the receiver can operate without interruption or delay cycles and the transmitted data is communicated without any data being lost.
Highly integrated semiconductor circuits are increasingly important, particularly in producing battery operated devices such as cell phones, portable computers such as laptops, notebook computers and PDAs, wireless email terminals, MP3 audio and video players, portable wireless web browsers and the like, and these sophisticated integrated circuits increasingly include on-board data storage. Some integrated circuits are essentially one chip systems, and may be referred to as “SOICs” (System on an integrated circuit) or “SOCs” (Systems on a chip) devices. Because present day integrated circuits have many functions provided within one device, silicon area for each circuit within that device is very important. A large elastic buffer consumes substantial silicon area. For example, in the communications standard known as “PCI Express”, with 32 lanes, the receiver is required to have a 12×10×32 buffer. Implementing this buffer results in a requirement of 3840 flip flops; which requires a substantial silicon area. The bigger the elastic buffer, the more safety or margin exists for timing differences, that is, the less likely an underflow, or overflow, condition. However the demand for silicon area increases with increasing buffer size.
Thus, there is a continuing need for an efficient elastic buffer circuit and methods that provide effective data buffering with a reduced silicon area requirement.